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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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128K x 36 and 256K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
The MCM63P736 and MCM63P818 are 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache for the PowerPCTM and other high performance microprocessors. The MCM63P736 is organized as 128K words of 36 bits each and the MCM63P818 is organized as 256K words of 18 bits each. These devices integrate input registers, an output register, a 2-bit address counter, and high speed SRAM onto a single monolithic circuit for reduced parts count in cache data RAM applications. Synchronous design allows precise cycle control with the use of an external clock (K). Addresses (SA), data inputs (DQx), and all control signals except output enable (G), sleep mode (ZZ), and linear burst order (LBO) are clock (K) controlled through positive-edge-triggered noninverting registers. Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst addresses can be generated internally by the MCM63P736 and MCM63P818 (burst sequence operates in linear or interleaved mode dependent upon the state of LBO) and controlled by the burst address advance (ADV) input pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. Synchronous byte write (SBx), synchronous global write (SGW), and synchronous write enable (SW) are provided to allow writes to either individual bytes or to all bytes. The bytes are designated as "a", "b", etc. SBa controls DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte writes SBx are asserted with SW. All bytes are written if either SGW is asserted or if all SBx and SW are asserted. For read cycles, pipelined SRAMs output data is temporarily stored by an edge-triggered output register and then released to the output buffers at the next rising edge of clock (K). The MCM63P736 and MCM63P818 operate from a 3.3 V core power supply and all outputs operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC standard JESD8-5 compatible. * MCM63P736/MCM63P818-133 = 4 ns Access/7.5 ns Cycle (133 MHz) MCM63P736/MCM63P818-100 = 5 ns Access/10 ns Cycle (100 MHz) MCM63P736/MCM63P818-66 = 7 ns Access/15 ns Cycle (66 MHz) * 3.3 V + 10%, - 5% Core Power Supply, 2.5 V or 3.3 V I/O Supply * ADSP, ADSC, and ADV Burst Control Pins * Selectable Burst Sequencing Order (Linear/Interleaved) * Two-Cycle Deselect Timing * Internally Self-Timed Write Cycle * Byte Write and Global Write Control * Sleep Mode (ZZ) * PB1 Version 2.0 Compatible * JEDEC Standard 119-Pin PBGA and 100-Pin TQFP Packages
MCM63P736 MCM63P818
TQ PACKAGE TQFP CASE 983A-01
ZP PACKAGE PBGA CASE 999-01
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 10/8/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM63P736*MCM63P818 1
FUNCTIONAL BLOCK DIAGRAM
LBO ADV K ADSC ADSP K2
BURST COUNTER CLR 2
2
17/18
128K x 36 / 256K x 18 ARRAY
SA SA1 SA0
ADDRESS REGISTER
17/18
15/16
SGW SW WRITE REGISTER a
36/18
36/18
SBa
SBb
WRITE REGISTER b 4/2 WRITE REGISTER c* DATA-IN REGISTER K DATA-OUT REGISTER
SBc*
SBd*
WRITE REGISTER d*
K K2 K
WRITE REGISTER
SE1 SE2 SE3 G ZZ * Valid only for MCM63P736.
ENABLE REGISTER
ENABLE REGISTER
DQa - DQd / DQa - DQb
MCM63P736*MCM63P818 2
MOTOROLA FAST SRAM
MCM63P736 PIN ASSIGNMENTS
SA SA SE1 SE2 SBd SBc SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA DQc DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQd 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA TOP VIEW 119 BUMP PBGA TOP VIEW 100 PIN TQFP Not to Scale DQb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQa
1 A B C D E DQc F G DQc H J K DQd L DQd M DQc VDDQ NC NC DQc
2 SA SE2 SA DQc DQc
3 SA SA SA VSS VSS VSS SBc VSS NC VSS SBd VSS VSS VSS LBO SA NC
4 ADSP ADSC VDD NC SE1 G ADV SGW VDD K NC SW SA1 SA0 VDD SA NC
5 SA SA SA VSS VSS VSS SBb VSS NC VSS SBa VSS VSS VSS NC SA NC
6 SA SE3 SA DQb DQb
7 VDDQ NC NC DQb DQb
VDDQ DQc DQc DQc
DQb VDDQ DQb DQb DQb DQb
VDDQ VDD DQd DQd
VDD VDDQ DQa DQa DQa DQa
VDDQ DQd N P R T NC U VDDQ NC NC DQd DQd NC DQd DQd SA
DQa VDDQ DQa DQa SA NC DQa DQa NC ZZ
NC VDDQ
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 3
MCM63P736 PBGA PIN DESCRIPTIONS
Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d).
4A
ADSP
Input
4G (a) 6K, 7K, 6L, 7L, 6M, 6N, 7N, 6P, 7P (b) 6D, 7D, 6E, 7E, 6F, 6G, 7G, 6H, 7H (c) 1D, 2D, 1E, 2E, 2F, 1G, 2G, 1H, 2H (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 4F
ADV DQx
Input I/O
G
Input
Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter (68K/PowerPC). High -- interleaved burst counter (486/i960/Pentium). Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
4K 3R
K LBO
Input Input
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T 4N, 4P
SA SA1, SA0
Input Input
5L, 5G, 3G, 3L (a) (b) (c) (d) 4E
SBx SE1
Input Input
2B 6B 4H
SE2 SE3 SGW
Input Input Input
4M
SW
Input
7T
ZZ
Input
4C, 2J, 4J, 6J, 4R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 2U, 3U, 4U, 5U, 6U
VDD VDDQ VSS NC
Supply Supply Supply --
MCM63P736*MCM63P818 4
MOTOROLA FAST SRAM
MCM63P736 TQFP PIN DESCRIPTIONS
Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b, c, d).
84
ADSP
Input
83 (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 86
ADV DQx
Input I/O
G
Input
Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter (68K/PowerPC). High -- interleaved burst counter (486/i960/Pentium). Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: these pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b, c, d). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
89 31
K LBO
Input Input
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 99, 100 36, 37
SA SA1, SA0
Input Input
93, 94, 95, 96 (a) (b) (c) (d) 98
SBx SE1
Input Input
97 92 88
SE2 SE3 SGW
Input Input Input
87
SW
Input
64
ZZ
Input
15, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 14, 16, 38, 39, 42, 43, 66
VDD VDDQ VSS NC
Supply Supply Supply --
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 5
MCM63P818 PIN ASSIGNMENTS
SA SA SE1 SE2 NC NC SBb SBa SE3 VDD VSS K SGW SW G ADSC ADSP ADV SA SA NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQb NC VSS VDDQ NC NC NC 100 99 98 97 9695 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 3738 39 40 41 42 43 44 4546 47 48 49 50 LBO SA SA SA SA SA1 SA0 NC NC VSS VDD NC NC SA SA SA SA SA SA SA TOP VIEW 119 BUMP PBGA TOP VIEW 100 PIN TQFP Not to Scale SA NC NC VDDQ VSS NC DQa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC N VSS C VDDQ NC NC NC
1 A B C D E NC F G NC H J K L M DQb VDDQ VDDQ NC NC DQb
2 SA SE2 SA NC DQb NC DQb NC
3 SA SA SA VSS VSS VSS SBb VSS NC VSS VSS VSS VSS VSS LBO SA NC
4 ADSP ADSC VDD NC SE1 G ADV SGW VDD K NC SW SA1 SA0 VDD NC NC
5 SA SA SA VSS VSS VSS VSS VSS NC VSS SBa VSS VSS VSS NC SA NC
6 SA SE3 SA DQa NC
7 VDDQ NC NC NC DQa
DQa VDDQ NC DQa DQa NC
VDDQ VDD NC DQb DQb NC
VDD VDDQ NC DQa NC DQa NC SA SA DQa NC VDDQ NC DQa NC ZZ
VDDQ DQb N P R T NC U VDDQ SA NC DQb NC NC NC DQb SA
NC VDDQ
MCM63P736*MCM63P818 6
MOTOROLA FAST SRAM
MCM63P818 PBGA PIN DESCRIPTIONS
Pin Locations 4B Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter (68K/PowerPC). High -- interleaved burst counter (486/i960/Pentium). Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
4A
ADSP
Input
4G (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P 4F
ADV DQx G
Input I/O Input
4K 3R
K LBO
Input Input
2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 2T, 3T, 5T, 6T 4N, 4P
SA SA1, SA0
Input Input
5L, 3G (a) (b) 4E
SBx SE1
Input Input
2B 6B 4H
SE2 SE3 SGW
Input Input Input
4M
SW
Input
7T
ZZ
Input
4C, 2J, 4J, 6J, 4R 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 3J, 5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 1R, 5R, 7R, 1T, 4T, 2U, 3U, 4U, 5U, 6U
VDD VDDQ VSS NC
Supply Supply Supply --
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 7
MCM63P818 TQFP PIN DESCRIPTIONS
Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a READ, WRITE, or chip deselect. Synchronous Address Status Processor: Active low, interrupts any ongoing burst and latches a new external address. Used to initiate a new READ or chip deselect (exception -- chip deselect does not occur when ADSP is asserted and SE1 is high). Synchronous Address Advance: Increments address count in accordance with counter type selected (linear/interleaved). Synchronous Data I/O: "x" refers to the byte being read or written (byte a, b). Asynchronous Output Enable Input: Low -- enables output buffers (DQx pins). High -- DQx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low -- linear burst counter (68K/PowerPC). High -- interleaved burst counter (486/i960/Pentium). Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. Synchronous Byte Write Inputs: "x" refers to the byte being written (byte a, b). SGW overrides SBx. Synchronous Chip Enable: Active low to enable chip. Negated high -- blocks ADSP or deselects chip when ADSC is asserted. Synchronous Chip Enable: Active high for depth expansion. Synchronous Chip Enable: Active low for depth expansion. Synchronous Global Write: This signal writes all bytes regardless of the status of the SBx and SW signals. If only byte write signals SBx are being used, tie this pin high. Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. If only byte write signals SBx are being used, tie this pin low. Sleep Mode: This active high asynchronous signal places the RAM into the lowest power mode. The ZZ pin disables the RAMs internal clock when placed in this mode. When ZZ is negated, the RAM remains in low power mode until it is commanded to READ or WRITE. Data integrity is maintained upon returning to normal operation. Core Power Supply. I/O Power Supply. Ground. No Connection: There is no connection to the chip.
84
ADSP
Input
83 (a) 58, 59, 62, 63, 68, 69, 72, 73, 74 (b) 8, 9, 12, 13, 18, 19, 22, 23, 24 86
ADV DQx G
Input I/O Input
89 31
K LBO
Input Input
32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 99, 100 36, 37
SA SA1, SA0
Input Input
93, 94 (a) (b) 98
SBx SE1
Input Input
97 92 88
SE2 SE3 SGW
Input Input Input
87
SW
Input
64
ZZ
Input
15, 41, 65, 91 4, 11, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 43, 51, 52, 53, 56, 57, 66, 75, 78, 79, 95, 96
VDD VDDQ VSS NC
Supply Supply Supply --
MCM63P736*MCM63P818 8
MOTOROLA FAST SRAM
TRUTH TABLE (See Notes 1 Through 5)
Next Cycle Deselect Deselect Deselect Deselect Deselect Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Continue Write Continue Write Suspend Write Suspend Write Address Used None None None None None External External Next Next Next Next Current Current Current Current External Next Next Current Current SE1 1 0 0 X X 0 0 X X 1 1 X X 1 1 0 X 1 X 1 SE2 X X 0 X 0 1 1 X X X X X X X X 1 X X X X SE3 X 1 X 1 X 0 0 X X X X X X X X 0 X X X X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 1 X 1 X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 0 1 1 1 1 ADV X X X X X X X 0 0 0 0 1 1 1 1 X 0 0 1 1 G3 X X X X X X X 1 0 1 0 1 0 1 0 X X X X X DQx High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z DQ High-Z DQ High-Z DQ High-Z DQ High-Z High-Z High-Z High-Z High-Z Write 2, 4 X X X X X X5 READ5 READ READ READ READ READ READ READ READ WRITE WRITE WRITE WRITE WRITE
NOTES: 1. X = Don't Care. 1 = logic high. 0 = logic low. 2. Write is defined as either 1) any SBx and SW low or 2) SGW is low. 3. G is an asynchronous signal and is not sampled by the clock K. G drives the bus immediately (tGLQX) following G going low. 4. On write cycles that follow read cycles, G must be negated prior to the start of the write cycle to ensure proper write data setup times. G must also remain negated at the completion of the write cycle to ensure proper write data hold times. 5. This read assumes the RAM was previously deselected.
ASYNCHRONOUS TRUTH TABLE
Operation Read Read Write Deselected Sleep ZZ L L L L H G L H X X X I/O Status Data Out (DQx) High-Z High-Z High-Z High-Z
LINEAR BURST ADDRESS TABLE (LBO = VSS)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X10 X . . . X11 X . . . X00 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X00 X . . . X01 X . . . X10
INTERLEAVED BURST ADDRESS TABLE (LBO = VDD)
1st Address (External) X . . . X00 X . . . X01 X . . . X10 X . . . X11 2nd Address (Internal) X . . . X01 X . . . X00 X . . . X11 X . . . X10 3rd Address (Internal) X . . . X10 X . . . X11 X . . . X00 X . . . X01 4th Address (Internal) X . . . X11 X . . . X10 X . . . X01 X . . . X00
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 9
WRITE TRUTH TABLE
Cycle Type Read Read Write Byte a Write Byte b Write Byte c (See Note 1) Write Byte d (See Note 1) Write All Bytes Write All Bytes NOTE: 1. Valid only for MCM63P736. SGW H H H H H H H L SW H L L L L L L X SBa X H L H L H L X SBb X H H L H L L X SBc (See Note 1) X H H H L H L X SBd (See Note 1) X H H H H L L X
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Power Supply Voltage I/O Supply Voltage Input Voltage Relative to VSS for Any Pin Except VDD Input Voltage (Three-State I/O) Output Current (per I/O) Package Power Dissipation Ambient Temperature Die Temperature Temperature Under Bias Storage Temperature Symbol VDD VDDQ Vin, Vout VIT Iout PD TA TJ Tbias Tstg Value VSS - 0.5 to + 4.6 VSS - 0.5 to VDD VSS - 0.5 to VDD + 0.5 VSS - 0.5 to VDDQ + 0.5 20 1.6 0 to 70 110 - 10 to 85 - 55 to 125 Unit V V V V mA W C C C C 3 3 2 2 2 Notes This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 2. This is a steady-state DC parameter that is in effect after the power supply has achieved its nominal operating level. Power sequencing is not necessary. 3. Power dissipation capability is dependent upon package characteristics and use environment. See Package Thermal Characteristics.
PACKAGE THERMAL CHARACTERISTICS -- PBGA
Rating Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single Layer Board Four Layer Board Symbol RJA RJB RJC Max 38 22 14 5 Unit C/W C/W C/W Notes 1, 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MCM63P736*MCM63P818 10
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS: 2.5 V I/O SUPPLY (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage I/O Pins Symbol VDD VDDQ VIL VIH VIH2 Min 3.135 2.375 - 0.3 1.7 1.7 Typ 3.3 2.5 -- -- -- Max 3.6 2.9 0.7 VDD + 0.3 VDDQ + 0.3 Unit V V V V V
RECOMMENDED OPERATING CONDITIONS: 3.3 V I/O SUPPLY (Voltages Referenced to VSS = 0 V)
Parameter Supply Voltage I/O Supply Voltage Input Low Voltage Input High Voltage Input High Voltage I/O Pins VIH Symbol VDD VDDQ VIL VIH VIH2 Min 3.135 3.135 - 0.5 2 2 Typ 3.3 3.3 -- -- -- Max 3.6 VDD 0.8 VDD + 0.5 VDDQ + 0.5 Unit V V V V V
VSS
VSS - 1.0 V
20% tKHKH (MIN)
Figure 1. Undershoot Voltage
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 11
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter Input Leakage Current (0 V Vin VDD) Output Leakage Current (0 V Vin VDDQ) AC Supply Current (Device Selected, All Outputs Open, Freq = Max) Includes VDD and VDDQ MCM63P736/818-133 MCM63P736/818-100 MCM63P736/818-66 Symbol Ilkg(I) Ilkg(O) IDDA Min -- -- -- Typ -- -- -- Max 1 1 TBD Unit A A mA 2, 3, 4 Notes 1
CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels) Sleep Mode Standby Current (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max, All Other Inputs Static at CMOS Levels, ZZ VDD - 0.2 V. TTL Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels) Clock Running (Device Deselected, Freq = Max, VDD = Max, VDDQ = Max, All Inputs Toggling at CMOS Levels) MCM63P736/818-133 MCM63P736/818-100 MCM63P736/818-66
ISB2 IZZ
-- --
-- --
TBD 2
mA mA
5, 6 1, 5, 6
ISB3 ISB4
-- --
-- --
TBD TBD
mA mA
5, 7 5, 6
Static Clock Running (Device Deselected, MCM63P736/818-166 Freq = Max,VDD = Max, VDDQ = Max, MCM63P736/818-150 All Inputs Static at TTL Levels) MCM63P736/818-133 Output Low Voltage (IOL = 2 mA) VDDQ = 2.5 V Output High Voltage (IOL = - 2 mA) VDDQ = 2.5 V Output Low Voltage (IOL = 8 mA) VDDQ = 3.3 V Output High Voltage (IOL = - 4 mA) VDDQ = 3.3 V
ISB5
--
--
TBD
mA
5, 6
VOL VOH VOL2 VOH2
-- 1.7 -- 2.4
-- -- -- --
0.7 -- 0.4 --
V V V V
NOTES: 1. LBO and ZZ pins have an internal pullup and will exhibit leakage currents of 5 A. 2. Reference AC Operating Conditions and Characteristics for input and timing. 3. All addresses transition simultaneously low (LSB) then high (MSB). 4. Data states are all zero. 5. Device is deselected as defined by the Truth Table. 6. CMOS levels for I/O's are VIT VSS + 0.2 V or VDDQ - 0.2 V. CMOS levels for other inputs are Vin VSS + 0.2 V or VDD - 0.2 V. 7. TTL levels for I/O's are VIT VIL or VIH2. TTL levels for other inputs are Vin VIL or VIH.
MCM63P736*MCM63P818 12
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, - 5%, TA = 0 to 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . 1.25 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . 1.0 V/ns (20 to 80%) Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 V Output Load . . . . . . . . . . . . . . See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1 and 2)
MCM63P736-133 MCM63P818-133 Parameter P Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Output Enable to Output Valid Clock High to Output Active Clock High to Output Change Output Enable to Output Active Output Disable to Q High-Z Clock High to Q High-Z Setup Times: Address ADSP, ADSC, ADV Data In Write Chip Enable Address ADSP, ADSC, ADV Data In Write Chip Enable Symbol S bl tKHKH tKHKL tKLKH tKHQV tGLQV tKHQX1 tKHQX2 tGLQX tGHQZ tKHQZ tADKH tADSKH tDVKH tWVKH tEVKH tKHAX tKHADSX tKHDX tKHWX tKHEX Min 7.5 3 3 -- -- 0 1.5 0 -- 1.5 2 Max -- -- -- 4 3.8 -- -- -- 3.8 7.5 -- MCM63P736-100 MCM63P818-100 Min 10 4 4 -- -- 0 1.5 0 -- 1.5 2 Max -- -- -- 5 4 -- -- -- 4 10 -- MCM63P737-66 MCM63P819-66 Min 15 6 6 -- -- 0 1.5 0 -- 1.5 2 Max -- -- -- 7 6 -- -- -- 6 15 -- Unit Ui ns ns ns ns ns ns ns ns ns ns ns 4, 5 4 4, 5 4, 5 4, 5 3 3 Notes N
Hold Times:
0.5
--
0.5
--
0.5
--
ns
NOTES: 1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP or ADSC is asserted. 2. All read and write cycle timings are referenced from K or G. 3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels. 4. This parameter is sampled and not 100% tested. 5. Measured at 200 mV from steady state.
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 13
OUTPUT Z0 = 50 RL = 50 1.25 V
Figure 2. AC Test Load
5 CLOCK ACCESS TIME DELAY (ns)
4
OUTPUT CL
3 2
1
0 0 20 40 60 80 100 LUMPED CAPACITANCE, CL (pF)
Figure 3. Lumped Capacitive Load and Typical Derating Curve
OUTPUT LOAD
OUTPUT BUFFER
TEST POINT
UNLOADED RISE AND FALL TIME MEASUREMENT INPUT WAVEFORM 2.0 0.5 2.0 0.5
OUTPUT WAVEFORM
2.0 0.5 tr tf
2.0 0.5
NOTES: 1. Input waveform has a slew rate of 1 V/ns. 2. Rise time is measured from 0.5 to 2.0 V unloaded. 3. Fall time is measured from 2.0 to 0.5 V unloaded.
Figure 4. Unloaded Rise and Fall Time Characterization
MCM63P736*MCM63P818 14
MOTOROLA FAST SRAM
2.9 2.5 PULL-UP VOLTAGE (V) - 0.5 0 0.8 1.25 1.5 2.3 2.7 2.9 I (mA) MIN - 38 - 38 - 38 - 26 - 20 0 0 0 I (mA) MAX - 105 - 105 - 105 - 83 - 70 - 30 - 10 0 0 0 - 38 CURRENT (mA) - 105 VOLTAGE (V) VOLTAGE (V) 2.3 2.1
1.25 0.8
(a) Pull-Up for 2.5 V I/O Supply
3.6
PULL-UP VOLTAGE (V) - 0.5 0 1.4 1.65 2.0 3.135 3.6 I (mA) MIN - 50 - 50 - 50 - 46 - 35 0 0 I (mA) MAX - 150 - 150 - 150 - 130 - 101 - 25 0
3.135 2.8
1.5 1.4
0 0 - 100 - 50 CURRENT (mA) - 150
(b) Pull-Up for 3.3 V I/O Supply
VDD I (mA) MAX 0 0 VOLTAGE (V) 20 40 63 80 80 80 80 0.3 0 0 40 CURRENT (mA) 80 1.6 1.25
PULL-DOWN VOLTAGE (V) - 0.5 0 0.4 0.8 1.25 1.6 2.8 3.2 3.4 I (mA) MIN 0 0 10 20 31 40 40 40 40
(c) Pull-Down Figure 5. Typical Output Buffer Characteristics
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 15
READ/WRITE CYCLES
tKHKL tKLKH
tKHKH
K
MCM63P736*MCM63P818 16
B C D t KHQV BURST WRAPS AROUND Q(A) tKHQX2 Q(B) Q(B+1) Q(B+2) Q(B+3) tGHQZ Q(B) D(C) D(C+1) D(C+2) D(C+3) tGLQX ADSP, SA SE2, SE3 IGNORED BURST READ BURST WRITE Q(D) SINGLE READ
SA
A
ADSP
ADSC
ADV
SE1
E
W
G
t KHQV
DQx
Q(n)
tKHQX1
tKHQZ
DESELECTED
SINGLE READ
MOTOROLA FAST SRAM
NOTE: E low = SE2 high and SE3 low. W low = SGW low and/or SW and SBx low.
EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE EEEEEEEEEEEEEE
tZZQZ tZZS
EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEEEE
I ZZ tZZREC
MOTOROLA FAST SRAM
ADV ADS DQ ZZ W G E K ADDR NORMAL OPERATION NO NEW READS OR WRITES ALLOWED
MCM63P736*MCM63P818 17
IDD NOTE: ADS low = ADSC low or ADSP low. ADS high = both ADSC, ADSP high. E low = SE1 low, SE2 high, SE3 low. IZZ (max) specifications will not be met if inputs toggle.
SLEEP MODE TIMING
IN SLEEP MODE NO READS OR WRITES ALLOWED NORMAL OPERATION
APPLICATION INFORMATION
SLEEP MODE A sleep mode feature, the ZZ pin, has been implemented on the MCM63P736 and MCM63P818. It allows the system designer to place the RAM in the lowest possible power condition by asserting ZZ. The sleep mode timing diagram shows the different modes of operation: Normal Operation, No READ/WRITE Allowed, and Sleep Mode. Each mode has its own set of constraints and conditions that are allowed. Normal Operation: All inputs must meet setup and hold times prior to sleep and t ZZREC nanoseconds after recovering from sleep. Clock (K) must also meet cycle, high, and low times during these periods. Two cycles prior to sleep, initiation of either a read or write operation is not allowed. No READ/WRITE: During the period of time just prior to sleep and during recovery from sleep, the assertion of either ADSC, ADSP, or any write signal is not allowed. If a write operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM can not be guaranteed immediately after ZZ is asserted (prior to being in sleep). Sleep Mode: The RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All inputs are allowed to toggle -- the RAM will not be selected and perform any reads or writes. However, if inputs toggle, the IZZ (max) specification will not be met. NON-BURST SYNCHRONOUS OPERATION Although this BurstRAM has been designed for PowerPC- and Pentium-based systems, these SRAMs can be used in other high speed L2 cache or memory applications that do not require the burst address feature. Most L2 caches designed with a synchronous interface can make use of the MCM63P736 and MCM63P818. The burst counter feature of the BurstRAMs can be disabled, and the SRAMs can be configured to act upon a continuous stream of addresses. See Figure 6. CONTROL PIN TIE VALUES (H VIH, L VIL)
Non-Burst Sync Non-Burst, Pipelined SRAM ADSP H ADSC L ADV H SE1 L LBO X
NOTE: Although X is specified in the table as a don't care, the pin must be tied either high or low.
K
ADDR
A
B
C
D
E
F
G
H
W
G
DQ
Q(A)
Q(B)
Q(C)
Q(D)
D(E)
D(F)
D(G)
D(H)
READS
WRITES
Figure 6. Configured as Non-Burst Synchronous SRAM
MCM63P736*MCM63P818 18
MOTOROLA FAST SRAM
ORDERING INFORMATION
(Order by Full Part Number) MCM
Motorola Memory Prefix Part Number
63P736 63P818
XX
X
X
Blank = Trays, R = Tape and Reel Speed (133 = 133 MHz, 100 = 100 MHz, 66 = 66 MHz) Package (TQ = TQFP, ZP = PBGA)
Full Part Numbers -- MCM63P736TQ133 MCM63P736TQ133R MCM63P736ZP133 MCM63P736ZP133R MCM63P818TQ133 MCM63P818TQ133R MCM63P818ZP133 MCM63P818ZP133R
MCM63P736TQ100 MCM63P736TQ100R MCM63P736ZP100 MCM63P736ZP100R MCM63P818TQ100 MCM63P818TQ100R MCM63P818ZP100 MCM63P818ZP100R
MCM63P736TQ66 MCM63P736TQ66R MCM63P736ZP66 MCM63P736ZP66R MCM63P818TQ66 MCM63P818TQ66R MCM63P818ZP66 MCM63P818ZP66R
PACKAGE DIMENSIONS
ZP PACKAGE 7 x 17 BUMP PBGA CASE 999-01
4X PIN 1A IDENTIFIER
0.20 (0.008)
A -W-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER.
7 6 54 3 2 1 A B C D E F G H J K L M N P R T U
P
B -L-
S
16X
G
DIM A B C D E F G K N P R S 119X
MILLIMETERS MIN MAX 14.00 BSC 22.00 BSC --- 2.40 0.60 0.90 0.50 0.70 1.30 1.70 1.27 BSC 0.80 1.00 11.90 12.10 19.40 19.60 7.62 BSC 20.32 BSC
INCHES MIN MAX 0.551 BSC 0.866 BSC --- 0.094 0.024 0.035 0.020 0.028 0.051 0.067 0.050 BSC 0.031 0.039 0.469 0.476 0.764 0.772 0.300 BSC 0.800 BSC
N TOP VIEW
6X
G R BOTTOM VIEW
D 0.30 (0.012) 0.10 (0.004)
S S
TW T
S
L
S
F C
0.25 (0.010) T 0.35 (0.014) T 0.15 (0.006) T -T- K E SIDE VIEW
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MOTOROLA FAST SRAM
MCM63P736*MCM63P818 19
TQ PACKAGE TQFP CASE 983A-01
4X
e 0.20 (0.008) H A-B D
2X 30 TIPS
0.20 (0.008) C A-B D -D-
80 81 51 50
e/2
B E/2 B VIEW Y E1 E E1/2
BASE METAL PLATING
-A-
-B-
-X- X=A, B, OR D
b1 c
100 1 30
31
D1/2 D1 D
2X 20 TIPS
D/2
0.13 (0.005)
0.20 (0.008) C A-B D
A -H- -C-
SEATING PLANE
q
2
0.10 (0.004) C
q
3 VIEW AB
0.05 (0.002)
S
S
q
1 0.25 (0.010)
GAGE PLANE
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS D1 AND B1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE b DIMENSION TO EXCEED 0.45 (0.018). MILLIMETERS MIN MAX --- 1.60 0.05 0.15 1.35 1.45 0.22 0.38 0.22 0.33 0.09 0.20 0.09 0.16 22.00 BSC 20.00 BSC 16.00 BSC 14.00 BSC 0.65 BSC 0.45 0.75 1.00 REF 0.50 REF 0.20 --- 0.08 --- 0.08 0.20 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _ INCHES MIN MAX --- 0.063 0.002 0.006 0.053 0.057 0.009 0.015 0.009 0.013 0.004 0.008 0.004 0.006 0.866 BSC 0.787 BSC 0.630 BSC 0.551 BSC 0.026 BSC 0.018 0.030 0.039 REF 0.020 REF 0.008 --- 0.003 --- 0.003 0.008 0_ 7_ 0_ --- 11 _ 13 _ 11 _ 13 _
A2
R2
A1
R1
L2 L L1 VIEW AB
q
DIM A A1 A2 b b1 c c1 D D1 E E1 e L L1 L2 S R1 R2
q
1 2 q3
q q
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MCM63P736*MCM63P818 20
EEEE CCCC EEEE CCCC
b
M
c1
C A-B
S
D
S
SECTION B-B
Mfax is a trademark of Motorola, Inc.
MCM63P736/D MOTOROLA FAST SRAM

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